1. Field of the Invention
The invention relates to a thin film transistor (TFT), and more particularly to a thin film transistor with a self-aligned lightly-doped region and a fabrication method thereof.
2. Description of the Related Art
Thin film transistors (TFTs) are used in a variety of integrated circuits, and in particular, as a switching device in each pixel area of liquid crystal display (LCD) and OLED display. According to the materials used, a TFT is classified as either an amorphous silicon TFT or a polysilicon TFT. Compared with the amorphous TFT, the polysilicon TFT has the advantages of high carrier mobility, high integration of driving circuits, small leakage current and higher speed operation, and is often applied to high-speed operation applications, such as a static random access memory (SRAM). One of the major problems of these TFTs is the OFF-state leakage current, which causes charge loss in LCDs and high standby power dissipation in SRAMs. Seeking to solve this problem, conventional lightly doped regions have been used to reduce the drain junction field, thereby reducing the leakage current.
FIGS. 1A and 1B are cross-sectional diagrams showing a conventional method of forming a lightly doped region on a poly-Si TFT.
In FIG. 1A, a polysilicon layer 12 is formed on a predetermined surface of a transparent insulating substrate 10, and then a gate insulating layer 14 is formed on the polysilicon layer 12. Next, using a patterned photoresist layer 16 as a mask, a heavy ion implantation process 17 is performed to form an N+ doped region 18 on the polysilicon layer 12, thus serving as a source/drain region.
In FIG. 1B, after removing the patterned photoresist layer 16, a gate layer 20 is patterned on the gate insulating layer 14 to cover a part of the undoped regions of the polysilicon layer 12. Next, using the gate layer 20 as a mask, a light ion implantation process 21 is performed to form an N− doped region 22 on the undoped region of the polysilicon layer 12. The N− doped region 22 serves as a lightly doped region, and the undoped region of the polysilicon layer 12 underlying the gate layer 20 serves as a channel region.
The above-described method uses the patterned photoresist layer 16 to define the source/drain region, and uses the gate layer 20 to define the lightly doped region. With regard to the limitations of the exposure technique, a problem of photo misalignment easily occurs and may lead to a shift of the gate layer 20, resulting in a shift of the lightly doped region. Also, since two steps of ion implantation processes 17 and 21 are required, the shift problem is worsened, and the complexity of the process, the production cost, and the process time are increased. Moreover, the length of the channel region may vary due to shifting of the lightly doped region, thus the scale reducibility of the polysilicon TFT and the electric performance of the channel region are not reliable.
FIGS. 2A to 2C are cross-sectional diagrams showing another conventional method of forming a lightly doped region structure on a poly-Si TFT. In FIG. 2A, a polysilicon layer 32, a gate insulating layer 34 and a gate layer 36 are successively formed on a transparent insulating substrate 30. Then, using a first photoresist layer 38 as a mask, the gate layer 36 and the gate insulating layer 34 are etched to expose a predetermined region of the polysilicon layer 32.
Hereinafter, the method of forming the LDD (lightly doped drain) structure is used in N-MOS poly-Si TFT applications. In FIG. 2B, after removing the first photoresist layer 38, the gate layer 20 is used as a mask, and a light ion implantation process 39 is performed to form an N− doped region 40 on the exposed region of the polysilicon layer 32.
Next, in FIG. 2C, a second photoresist layer 42 is formed to cover the top and the sidewall of the gate layer 36 and the gate insulating layer 34, thus covering a portion of the N− doped region 40 laterally adjacent to the gate layer 36. Finally, using the second photoresist layer 42 as a mask, a heavy ion implantation process 43 is performed to form an N+ doped region 44 on the exposed area of the N− doped region 40. Thus, the N+ doped region 44 serves as a source/drain region, the remaining portion of the N− doped region 40 serves as an LDD structure, and the polysilicon layer 32 underlying the gate layer 36 serves as a channel region.
The above-described method prevents the shift of the LDD structure from the shift of the gate layer 36 caused by the photo misalignment. The shift of the second photoresist layer 42 and two steps of the ion implantation processes 39 and 43, however, still worsen the shift problem of the LDD structure.